In applications with power inverters having free-wheeling diodes, a commonly known negative effect is related to the commutation of the current from a free-wheeling diode to the switching transistor. FIG. 1 illustrates inverter bridge leg circuit 100 with high-side switch 101, low-side switch 102, diodes 103, 104 and load 105. When high-side switch 101 is opened, free-wheeling diode 104 takes over the load current IL. When high-side switch 101 is closed again, such as for the next switching period, a current peak takes place. This current peak results from the fact that diode 104 cannot immediately block the current at the beginning of the commutation phase. As a result, the current peak appears due to a short circuit of the inverter bridge leg. The current peak is related to the time required for diode 104 to get rid of internal charge carriers. It is desirable to lower this current peak as much as possible to reduce switching stress and Electromagnetic Interference (EMI).
High-side switch 101 and low-side switch 102 may be metal-oxide-semiconductor field-effect transistors (MOSFET) or insulated-gate bipolar transistors (IGBT), for example. FIG. 2 illustrates exemplary current and voltage levels across a MOSFET transistor switch during the commutation phase of circuit 100 (FIG. 1). Curve 201 represents the current through high-side switch 101. Curve 202 represents the voltage over high-side switch 101. Curve 203 represents the gate voltage at high-side switch 101 and defines the switching instant.
The gate current is delivered by a gate driver. The slew rate of the current through the high-side switch 101 or the low-side switch 102 is defined using the current when the gate voltage reaches the threshold level just before the Miller plateau (i.e. the start of phase 2 illustrated in FIG. 3). If the gate current is too high, the switch starts conducting very fast and current peak 204 appears. To reduce current peak 204, the gate current at high-side switch 101 (FIG. 1) has to be reduced.
The gate current must be set to a value that fits the actual current load. The load current defines how fast the diode is able to block current. A higher load current results in faster blocking, which reduces the current peak. The easiest way to reduce the gate current is to adapt the gate current driver by adding a series resistance between the output stage of the gate driver and gate of the switch. If the series resistance between the gate driver output state and the gate of the switch transistor is too low, then a current peak will occur. If the series resistance between the gate driver output stage and the switch transistor gate is too high, then the switching will take longer and switching loss will increase. Furthermore, a high series resistance leads to a longer phase 1 (as illustrated in FIG. 3) and in an undesirable switching delay.
One disadvantage of the prior art is that the gate current capability is typically adapted to a nominal load current and cannot be adjusted dynamically. As a result, a current peak is created at lower loads and switching losses appear at higher loads.